Counters are common sequential logic circuits that create specific reoccurring output sequences, typically rising or falling binary numbers. FIG. 1 (prior art) depicts a conventional three-bit synchronous counter 100 that counts from zero (binary 000) to seven (binary 111). Counter 100 includes a count terminal CNT and three output terminals A, B, and C. Counter 100 increments upon receipt of each rising edge of a clock signal CLK on count terminal CNT. Counter 100 produces a three-bit binary signal B2-B0, where B0 represents the least-significant bit (LSB) and B2 represents the most-significant bit (MSB). Because counter 100 is synchronous, the updated output signals on terminals A, B, and C are available substantially simultaneously after counter 100 increments.
Synchronous counter 100 includes three sequential storage elements, flip-flops 105, 110, and 115. The synchronous xe2x80x9cDxe2x80x9d input terminal of flip-flop 105 connects to its own output terminal; the subsequent state for flip-flop 105 therefore depends upon its current state. The subsequent state of flip-flop 110 depends on its current state and the state of flip-flop 105. The logic required to provide the second bit therefore includes some combinatorial logic 120 that produces an input to flip-flop 110 based upon the contents of flip-flops 105 and 110. Finally, the subsequent state of the MSB stored in flip-flop 115 depends upon its own state and the states of the two lower order flip-flops 105 and 110. The D input of flip-flop 115 consequently includes more complex combinatorial logic 125 that derives the input of flip-flop 115 from the contents of all three flip-flops 105, 110, and 115.
Each time a bit is added to a synchronous counter of the type shown in FIG. 1, the combinatorial logic required to derive the input signal for the most significant bit grows more complex. This increase in complexity requires valuable real estate and reduces counting speed. Using faster circuits for the combinatorial logic can offset this speed reduction, but faster circuits consume more power, and are therefore undesirable. It can therefore be very difficult to produce high-speed synchronous counters with the significant number of bits.
FIG. 2 (prior art) depicts a conventional three-bit ripple counter 200, which includes three flip-flops 205, 210, and 215. Ripple counters, in general, are capable of counting much faster than synchronous counters. This performance advantage is due to the fact that the input of each of flip-flop depends only on that flip-flops current state, so there is no need for the relatively complex combinatorial logic associated with synchronous counters. Unfortunately, the outputs provided by ripple counter 200 are not synchronous; that is, when counter 200 moves from one count to the next, the new value for the least significant bit (output Q0) is available before the new value for the next-most significant bit (output Q1), which is available before the new value for the most significant bit (output Q2). Ripple counter 200 thus changes from one value to the next (updates) relatively slowly. The time required for a counter to change from one value to the next is the counter""s xe2x80x9clatency.xe2x80x9d The maximum counting frequency of ripple counters remains relatively constant as the number of bits increases, but the latency rises linearly.
Returning to FIG. 1, the update speed of synchronous counter 100 is determined by the clock-to-out delay of flip-flop 115 and the delay through combinatorial logic circuit 125, which is presumed to be the slowest path in counter 100. For a small counter, such as the one shown, the combinatorial logic does not impose a significant delay; however, the complexity of the requisite combinatorial logic increases exponentially with the number of bits. Consequently, both the counting frequency and the latency are adversely affected by increases in the number of bits.
The latency of ripple counters renders them unsuitable for many applications. Synchronous counters are better, but the exponential growth in the required combinatory logic makes it difficult or impossible to strike an optimal balance between power, speed, and the number of bits for applications that require relatively large and fast synchronous counters. There is therefore a need for improved synchronous counters.
The present invention addresses the need for improved synchronous counters. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register can then be rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2xe2x80x3 synchronous storage elements. Two or more of the foregoing counters can be chained together in series to produce larger synchronous counters. When thus combined, the number of synchronous storage elements grows linearly with the number of bits.
The most significant bits of conventional synchronous counters are the most logic intensive, and consequently have the biggest adverse impact on power consumption, area, and speed performance. One embodiment combines a ripple counter and a synchronous counter to reduce this impact. A ripple counter is used for one or more lower-order bits and a synchronous counter for the higher-order bits. The number of bits in the synchronous counter, and thus the combinatorial-logic overhead, is reduced by the number of bits in the ripple counter.
An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.
This summary does not limit the invention, which is instead defined by the allowed claims.